1. Field of the Invention
The present invention relates to power transistors, more particularly to radio frequency (RF) power transistors of the silicon bipolar type. Such transistors are commonly used in amplification stages for radio base station amplifiers, but are also widely used in other RF-related applications.
2. State of the Art
Transistor devices used for power amplifications at high frequencies need to meet numerous detailed requirements for output power, gain, ruggedness, efficiency, stability, bandwidth, etc., at a specified supply voltage and operating frequency. The operating frequencies for modem telecommunication electronics range from several hundred megahertz up into the microwave region. The output power requirements range from a few watts up to several hundred watts, using many paralleled devices in one package. Power transistors operate at large signal levels and high current densities. Computer tools presently available are often not sufficient to predict detailed behavior or performance in real applications.
The semiconductor material most commonly used for power transistors (at least for frequencies below 3 GHz) is silicon. Furthermore, because of the higher mobility of electrons as compared to holes, virtually all microwave bipolar transistors are of the NPN type. Epitaxial n on n+wafers are used as a starting material to reduce collector series resistance. An insulating layer is formed on the semiconductor surface, and base and emitter layers are formed by diffusion or ion implantation. Different doping profiles produce different frequency and breakdown voltage characteristics, and different horizontal geometries produce transistors of different current capabilities.
Interdigitated, overlay and mesh structures have been used to reduce the dimensions of the active areas of power transistors and reduce parasitics, to handle and distribute the large amount of current in the transistor, and to provide heat spreading. An interdigitated structure 10 is shown in FIGS. 1 and 2. Referring to FIG. 1, a pair of interdigitated base and emitter electrodes B and E, respectively, are deposited above an oxide layer overlying a collector diffusion region 11, indicated by dashed lines. As shown in FIG. 2, within the collector diffusion region 11 are located alternating base diffusion regions 13 and emitter diffusion regions 15 underlying the fingers of the base and emitter electrodes B and E, respectively. A transistor is formed by the collector substrate (N), a base diffusion region (P) and an emitter diffusion region (N). Metal emitter fingers 14 are deposited over the emitter diffusion regions and metal base fingers 16 are deposited over the base diffusion regions. All of the base fingers and all of the emitter fingers, respectively, are connected together such that all of the individual transistors are connected together in parallel.
Referring to FIGS. 3 and 4, the overlay structure differs from the interdigitated structure in that the diffusion regions (base and emitter) and the electrode fingers (base and emitter) are transverse to one another. The emitter electrode fingers are overlaid directly on the emitter diffusion regions and are separated from the base diffusion regions by a oxide layer The emitter diffusion regions are discontinuous so as to allow a base finger to pass between adjacent emitter diffusion regions and connect to different base diffusion regions. The base diffusion regions are continuous.
Referring to FIGS. 5 and 6, in a typical mesh structure power transistor, base diffusion islands 13 are formed within a surrounding emitter diffusion region 15. Two base diffusion regions are joined by adjacent base electrode fingers 14a and 14b on either side of an emitter electrode finger 16.
The physical dimensions and the internal metallization patterns of the RF power package in which a silicon die is placed affect the overall performance of the packaged transistor. As the operating frequency increases, degradation occurs in the overall performance of the packaged transistor. The causes of this degradation in performance are found in the silicon die and the transistor package, as well as the connections from the silicon die to the transistor package. Connection of the silicon die to the RF package is accomplished by a physical eutectic connection of the die to the package, and by connection of wires from the die to the appropriate lead of the RF package.
Often, the silicon die are operated in the attenuation region of the common-emitter gain curve so that a minor increase in the operating frequency can cause considerable degradation of gain and output power. Also, parasitic losses in the die increase with frequency.
As the operating frequency increases, the RF power transistor's package has the greatest influence on total performance. One of the main causes of performance degradation is common lead inductance of the emitter wires and package. At higher frequencies, the distance between the input and the output is generally decreased to minimize the amount of internal impedance matching required and to minimize common lead inductance to ground.
The common lead may be considered to be that lead which has the majority of the input and output current flowing through it. Common lead inductance refers to the inductance of the common lead caused by the length of the wire which connects the common element to ground. Although in some instances common lead inductance may actually be used to enhance performance, most often it degrades performance.
One of the dominant contributors to common lead inductance is the bonding wire between the emitter bond pad and common lead of the RF package. In the case of a common-emitter amplifier, the common lead of the package is the emitter lead.
A traditional metallization layout of a silicon cell 10' is shown in FIG. 7. Because of thermal instability in bipolar transistors, techniques must be used to evenly distribute the current in the transistor. Resistance is therefore added to each segment of the transistor, such that an increase in current through a particular emitter will be limited by the resistor. This technique is known as emitter ballasting. A resistor Re is formed in series with each emitter finger, either by diffusion, ion implantation, or deposition of a suitable metal (e.g., nickel-chromium, NiCr) on top of the silicon dioxide. All of the resistors are joined together by the emitter electrode E. An emitter bond pad 17 provides for bonding of a wire to the emitter electrode E. Similarly, all of the base fingers are joined together by the base electrode B, and a base bond pad 19 provides for bonding of a wire to the base electrode B.
As seen in FIG. 7, traditional silicon cell metallization layouts place the base and emitter bond pads 17 and 19 in the center of the cell 10'. Current is therefore coupled from the power supply to the base pad 19 over a distance. The emitter current consists of the combination of the base current and the collector current, which flows through the load to produce an output signal. The emitter current is coupled from the emitter pad 17 to ground over the same distance. Because of the length of the emitter wire and its proximity to the base wire, there is feedback of the load current to the source as a result of mutual inductive coupling of the base and emitter wires. Although a small amount of feedback current can be advantageous, if the length of the of emitter wire is long, deleterious effects occur. With the emitter pad in the center of the cell, the emitter wire must be at least as long as from the appropriate lead of the RF package to the center of the cell.
Furthermore, in conventional cell layout, more than one cell is located on a single block of silicon in order to conserve silicon. These cells are generally aligned such that the base and emitter wires of each cell are located in close proximity to each other. In FIG. 8, two transistor cells 20a and 20b occupy a single silicon die 30. The silicon die 30 is bonded to a "pill" 101 comprising a substrate (typically beryllium oxide) to which base, collector and emitter leads B, C and E are bonded. Chip capacitors and other elements used for impedence matching may also be bonded to the pill. The pill 101 is bonded in turn to a flange 103.
As shown in greater detail in FIG. 9, ground bars 21a and 21b are provided on two opposite sides of the die as part of the transistor package. In the case of the emitter bonding pads, two wires are connected to each emitter bonding pad, one (23a) from one of the ground bars and another (23b) from the opposite ground bar.
Referring again to FIG. 8, in the case of the base bonding pads, a single wire 23 is connected from each bonding pad to the base lead of the transistor package. When the emitter wires and the base wires are connected as shown in FIG. 8, in many cases the emitter wire is located sufficiently close to the base wire of the adjacent cell to couple false feedback currents to the adjacent cell via mutual inductive coupling.